(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of a planarized structure of polysilicon or other conductor materials embedded in an insulator.
The method of fabrication can, also, be used to fabricate polysilicon DRAM cylindrical capacitors for use in semiconductor integrated circuit devices.
(2) Description of related Art
In the fabrication of semiconductor integrated circuits CMP (Chemical Mechanical Polishing) can be used to remove different layers of material from the surface of a semi-conductor substrate. For example, following via hole formation in an insulating layer, a metallization layer is deposited and then CMP is used to produce planar metal plugs embedded in the insulating layer. Similarly, inter-connection wiring can be formed by first etching wiring channels into an insulating layer and then depositing a metallization layer onto the insulating layer and into the etched channels. CMP is then used to selectively remove the metallization layer from the surface of the insulating layer, leaving the metallization material embedded in the etched channels. Also, CMP has been developed for providing smooth topographies on insulating layers deposited on semiconductor substrates. It is desirable that the insulating layers have smooth topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
An important challenge in CMP, when selectively removing a second material layer from a first material layer, is to remove the second material without removing an excessive amount of the underlying first material layer. Also, it is important to not leave residues of the second material on the surface of the first material. Conventional practice is to utilize a polishing slurry which has high selectivity for removal of the second material layer over the first material layer, detecting when the surface of the first material layer is reached, and then in order to remove residues of the second material layer on the surface of the first material the conventional practice is to provide an over-polish period beyond the detected endpoint for removing the second material over the first material. This over-polish period, which may be 50 to 100% greater than the detected polishing endpoint, adds additional processing time and, therefore, additional cost. Furthermore, during the CMP over-polish period excessive amount of the underlying first material may be removed on some regions of the substrate and the within-cell and cell-to-periphery planarity could be degraded.
U.S. Pat. No. 5,498,562 entitled "Semiconductor Processing Methods Of Forming Stacked Capacitors" granted Mar. 12, 1996 to Charles H. Dennison et al describes a method of forming a stacked capacitor wherein the electrode is defined using a CMP (Chemical Mechanical Polishing) process. A multi-container stacked capacitor construction has its containers defined or otherwise electrically isolated in a single CMP (Chemical Mechanical Polishing) step.
U.S. Pat. No. 5,633,190 entitles "Semiconductor Device and Method For Making the Same" granted May 27, 1997 to Mitsuhiro Sugiyama shows a method of planarizing oxide over high and low regions.
U.S. Pat. No. 5,312,512 entitled "Global Planarization Using SOG and CMP" granted May 17, 1994 to Derryl D. J. Allman et al describes a method of planarizing metal lines using SOG (Spin On Glass) and CMP (Chemical Mechanical Polishing).
The present invention is directed to a novel method of using CMP to selectively remove a second material over a first material and produce a planar first material surface, free of second material residue. The method of the present invention requires less CMP processing time, has lower cost than conventional CMP methods and produces a polished surface having superior planarity.